tpolecat industries –

Testing Servos with a Function Generator

Wed, 23 Sep 2026 10:38:15 -0500

Very quick post about testing servos without a servo tester, mostly for my own reference but here you go.

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I occasionally build things with SG90 hobby servos and I like to hook them up and see them move without having to deal with a microcontroller. It’s easy to do with a function generator.

Control Signal

SG90 servos (and maybe others, I don’t know) are powered by 5V and have a third wire (orange), which is the control signal.

The control signal is a stream of 20ms pulses.
The length of these pulses determines servo demand.
Pulses vary between 1ms and 2ms in width, controlling 180° of movement.
Behavior outside these ranges is usually undefined, but most servos can go a few tens of degrees past the limits.

Function Generator Setup

Set up the function generator as follows:

Amplitide of 5V, offset +2.5V (i.e., swinging between 0V and +5V).
One of:
- pulse mode with a period of 20ms and width of 1.5ms; or
- square wave at 50Hz with duty cycle of 7.5%.

Wire up power and ground (red and brown) to the servo, connect the control wire (orange) to the function generator’s output, and connect function generator ground to the other ground wires. I made a little board so I can just plug everything in.

The servo should zero itself when you power up and start producing a signal. Adjust the pulse duration between 1ms and 2ms (or 5% and 10% duty cycle) to test range of movement.

GALs by Example, Part 3

Sat, 19 Sep 2026 09:28:53 -0500

In part two we learned how to use tri-state outputs to control access to and from a shared data bus. In this post we will learn how to implement sequential logic by using the GAL16V8 in registered mode.

Running out of ideas. Here's some salt and pepper shrimp.

GAL16V8 in Registered Mode

In registered mode we again have 16 inputs and 8 outputs, but the outputs can now be registered, meaning they do not output their values immediately, but rather latch these values on the rising edge of the clock (dedicated pin 1). All registered outputs share a single output-enable (dedicated pin 11). Here is the pinout in registered mode.

GAL16V8 in Registered Mode

At first glance it might appear that this mode is strictly better than complex mode, as tri-state outputs are still allowed in this mode (and none have the “no feedback” restriction). The catch is that while you can indeed have eight tri-state outputs in this mode, this would leave you with only eight inputs due to pins 1 and 11 being dedicated to CLK and /OE. In complex mode you would have ten inputs available. However as far as I can tell, GALasm will only select registered mode if there is at least one registered output, so this question may be academic.

A Parallel-Load Shift Register

A common task in electronics is turning serial data into a paralle data, which we do via a shift register. We will implement a 4-bit shift register with parallel load using a GAL16V8 in registered mode.

Bits shift in via SDIN on the rising edge of CLK, through bits Q0, Q1, Q2, Q3. SDOUT is identical to Q3. If /LOAD is asserted then the values on D[0:4] are copied to Q[0:4] on the rising clock. If /CLR is asserted then all bits are cleared on the rising clock.

Here is the GALasm source in its entirety.

shift.pld

GAL16V8
SHIFT
CLK /LOAD /CLR D3 D2 D1 D0 NC SDIN GND
/OE SDOUT NC Q3 Q2 Q1 Q0 NC NC VCC
Q0.R = /CLR & LOAD & D0
# /CLR & /LOAD & SDIN
Q1.R = /CLR & LOAD & D1
# /CLR & /LOAD & Q0
Q2.R = /CLR & LOAD & D2
# /CLR & /LOAD & Q1
Q3.R = /CLR & LOAD & D3
# /CLR & /LOAD & Q2
SDOUT.R = /CLR & LOAD & D3
# /CLR & /LOAD & Q2
DESCRIPTION
A 4-bit parallel load shift register.

Note the following:

We must specify CLK at pin 1 and /OE at pin 11. These are keyword labels like VCC and GND.
Registered outputs have the .R suffix. The value is latched on the rising CLK.
Much like tri-state outputs, we refer to the feedback from registered outputs without a suffix. These refer to current latched values, which we use to compute the next latched values.

Testing

Here is a test suite for the shift register. Note the use of the C token for pin 1. This instructs minipro to issue a positive-going clock pulse before checking the output bits. Agan, refer to the post on testing GALs for more information.

buffer.xml

<?xml version="1.0" encoding="utf-8"?>
<logicic>
 <database type="LOGIC">
 <custom name="whatever-you-want">
 <ic name="shift" type="5" voltage="5V" pins="20">

 <vector> C 01 1011 X X G 0 H X HLHH XXV </vector> <!-- Load -->
 <vector> X XX XXXX X X G 1 Z X ZZZZ XXV </vector> <!-- Disable -->
 <vector> X XX XXXX X X G 0 H X HLHH XXV </vector> <!-- Enable -->
 <vector> C 11 XXXX X 0 G 0 L X LHHL XXV </vector> <!-- Shift a 0 -->
 <vector> C 11 XXXX X 1 G 0 H X HHLH XXV </vector> <!-- Shift a 1 -->
 <vector> C 11 XXXX X 1 G 0 H X HLHH XXV </vector> <!-- Shift a 1 -->
 <vector> C X0 XXXX X X G 0 L X LLLL XXV </vector> <!-- Clear -->

 </ic>
 </custom>
 </database>
</logicic>

Exercises

Program two shift registers and chain them together through SDOUT and SDIN to create an 8-bit shift register.
Write a 4-bit counter.

GALs by Example, Part 2

Fri, 18 Sep 2026 09:43:53 -0500

In part one we learned about using the GAL16V8 in simple mode, which allows only pure combinational logic. In this post we will learn how to use tri-state logic in complex mode.

I couldn't find a photo to illustrate tri-state logic but we do have three cats.

In simple mode, outputs could only be high or low. In this post we introduce complex mode, which adds the possibility of outputs being individually disabled. Disabled ouputs retain feedback and can be used as inputs, so they are effectively bidirectional.

GAL16V8 in Complex Mode

In complex mode we still have 16 input pins and 8 output pins, but they are arranged slightly differently. Here is the pinout when in complex mode.

GAL16V8 in Complex Mode

Note that the pins 12 and 19 do not have feedback in this mode. This means they cannot be used in the right-hand side of an equation.

A Bidirectional Buffer

Many systems use a shared data bus, where components read and write to the same data lines. At any moment a component can be reading, writing, or ignoring the shared bus. A useful component to have in this situation is a bi-directional buffer with tri-state outputs, so that’s what we’re going to build.

Our buffer will gate access to a three-bit bus. Data can flow from A to B, from B to A, or can be disconnected entirely. This is like a 3-bit version of a 74LS245 bus transceiver.

A three-bit bidirectional buffer.

Our choice of pins is more constrained this time. The inputs on the left can go anywhere, but we need feedback on our tri-state outputs so we can only use the six middle pins on the right side.

Our GALasm prelude has the same format as in simple mode. Note that output OE is active low. DAB means “direction is from A to B”.

buffer.pld

GAL16V8
BUFFER
/OE DAB NC NC NC NC NC NC NC GND
NC NC A0 A1 A2 B0 B1 B2 NC VCC

The equations are a little different from what we saw in part one. Here are the equations for data flowing from A to B.

; A -> B when enabled and DAB is asserted
B0.T = A0
B1.T = A1
B2.T = A2
B0.EN = OE & DAB
B1.EN = OE & DAB
B2.EN = OE & DAB

Note the following:

We define a tri-state output by adding the .T suffix. This means that B0 will have A0’s value, but only when B0 is enabled.
For each tri-state output we use a second equation to specify when the output is enabled, via the .EN suffix. In this case the B outputs are all enabled when output is enabled and the direction is from A to B.
GALasm requires that each .T equation appear before its associated .E equation in the source file.

The B to A flow is defined analogously, swapping A and B and enabling output when DAB is not asserted. Here is our final source file.

buffer.pld

GAL16V8
BUFFER
/OE DAB NC NC NC NC NC NC NC GND
NC NC A0 A1 A2 B0 B1 B2 NC VCC
; A -> B when enabled and DAB is asserted
B0.T = A0
B1.T = A1
B2.T = A2
B0.EN = OE & DAB
B1.EN = OE & DAB
B2.EN = OE & DAB
; B -> A when enabled and DAB is disasserted
A0.T = B0
A1.T = B1
A2.T = B2
A0.EN = OE & /DAB
A1.EN = OE & /DAB
A2.EN = OE & /DAB
DESCRIPTION
A 3-bit bidirectional buffer.

Assembly and Programming

We assemble as we did in part one. The -v is optional but sometimes provides more output, which can be useful for debugging.

$ galasm -v buffer.pld
GALasm 2.1, Portable GAL Assembler
Copyright (c) 1998-2003 Alessandro Zummo. All Rights Reserved
Original sources Copyright (c) 1991-96 Christian Habermann
Assembler Phase 1 for "buffer.pld"
Assembler Phase 2 for "buffer.pld"
Using complex mode because:
pin 13 (A0) is configured as tri-state output
pin 14 (A1) is configured as tri-state output
pin 15 (A2) is configured as tri-state output
pin 16 (B0) is configured as tri-state output
pin 17 (B1) is configured as tri-state output
pin 18 (B2) is configured as tri-state output
GAL16V8; Operation mode: complex; Security fuse off
Assembling successfully completed.
$ _

Note that the operation mode has been inferred as complex due to the presence of tri-state outputs. Programming is the same as in part one.

$ minipro -p GAL16V8D -w buffer.jed
Found TL866II+ 04.2.123 (0x27b)
Warning: Firmware is out of date.
Expected 04.2.132 (0x284)
Found 04.2.123 (0x27b)
Device code: 02106811
Serial code: N95SXK8LUBRHLHXHQG4Y
USB speed: 12Mbps (USB 1.1)
VPP=16V
Declared fuse checksum: 0x3A5E Calculated: 0x3A5E ... OK
Declared file checksum: 0x990C Calculated: 0x990C ... OK
JED file parsed OK
Erasing... 0.83Sec OK
Writing jedec file... 3.45Sec OK
Reading device... 0.09Sec OK
Verification OK
$ _

Testing

Our testing strategy is the same as in part one, with one difference: when output is disabled we want to verify that the outputs are indeed high-impedance. For this we use the Z output state.

buffer.xml

<?xml version="1.0" encoding="utf-8"?>
<logicic>
 <database type="LOGIC">
 <custom name="whatever-you-want">
 <ic name="buffer" type="5" voltage="5V" pins="20">

 <!-- A to B -->
 <vector> 01 XXXXXXXG XX 000 LLL XV </vector>
 <vector> 01 XXXXXXXG XX 101 HLH XV </vector>
 <vector> 01 XXXXXXXG XX 111 HHH XV </vector>
 <vector> 11 XXXXXXXG XX 101 ZZZ XV </vector>

 <!-- B to A -->
 <vector> 00 XXXXXXXG XX LLL 000 XV </vector>
 <vector> 00 XXXXXXXG XX HLH 101 XV </vector>
 <vector> 00 XXXXXXXG XX HHH 111 XV </vector>
 <vector> 10 XXXXXXXG XX ZZZ 101 XV </vector>

 </ic>
 </custom>
 </database>
</logicic>

Note that disabled outputs retain a weak pull-up, so pins marked Z will measure high in isolation but will easily be swamped by active signals. Minipro detects this state by ensuring that the line can easily be pulled in either direction.

We run our tests as before.

$ minipro -T -p buffer --logicic buffer.xml
Using overridden database file buffer.xml
Found TL866II+ 04.2.123 (0x27b)
Warning: Firmware is out of date.
Expected 04.2.132 (0x284)
Found 04.2.123 (0x27b)
Device code: 02106811
Serial code: N95SXK8LUBRHLHXHQG4Y
USB speed: 12Mbps (USB 1.1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0000: 0 1 X X X X X X X G X X 0 0 0 L L L X V
0001: 0 1 X X X X X X X G X X 1 0 1 H L H X V
0002: 0 1 X X X X X X X G X X 1 1 1 H H H X V
0003: 1 1 X X X X X X X G X X 1 0 1 Z Z Z X V
0004: 0 0 X X X X X X X G X X L L L 0 0 0 X V
0005: 0 0 X X X X X X X G X X H L H 1 0 1 X V
0006: 0 0 X X X X X X X G X X H H H 1 1 1 X V
0007: 1 0 X X X X X X X G X X Z Z Z 1 0 1 X V
Logic test successful.
$ _

Exercises

Turn this into an inverting buffer.
Investigate the behavior of disabled outputs on a breadboard. Your 99¢ Logic Probe will show disabled lines as high. How strong is the pull-up?

GALs by Example, Part 1

Tue, 15 Sep 2026 13:45:18 -0500

GALs are simple programmable logic devices, (SPLDs) which are old technology but are still available and they remain popular among hobbysist as way to reduce the number of logic ICs in a project. Let’s learn how to use them!

Unlike their newer cousins the complex programmable logic devices (CPLDs), GALs can be programmed with open-source software and inexpensive hardware. Truly modern programmable logic is dominated by field programmable gate arrays (FPGAs), but these are much more complex, have limited open-source support, and require auxiliary circuity to support their operation. GALs are very limited when compared to their modern counterparts, but they are much, much easier to use.

Our basic workflow:

Write a source file.
Assemble it into a JEDEC file using GALasm.
Write the JEDEC file to a GAL using minipro.
Test the GAL, also using minipro.

GAL16V8 in Simple Mode

To me the GAL16V8 is the Arduino Uno of the GAL world. It’s a 20-pin device with 16 pins that can be used as inputs and 8 that can be used as outputs (hence the name). We’re going to start with the GAL16V8 and use it in its simplest mode, conveniently called “simple mode”, which allows only for combinational logic. Here is the pinout when used in simple mode.

GAL16V8 in Simple Mode

Writing a Logic Demo

As far as I know, nobody manufactures a logic chip providing an AND gate, an OR gate, an XOR gate, and a NOT gate. So let’s make one using a GAL16V8 in simple mode.

First let’s label our pins. We’ll need seven inputs and four outputs. I will use pins 1-7 for inputs (A-G) and 16-19 for outputs (Q*), but this is arbitrary and you can use any valid pins you like.

Pin labels for our logic demo.

Let’s start writing our GALasm source. At the top of the file we write a prelude that specifies our pin labels, as well as a few other things.

logidemo.pld

GAL16V8
LOGIDEMO
A B C D E F G NC NC GND
NC NC NC NC NC QG QEF QCD QAB VCC

Observe the following about the prelude:

The first line identifies the GAL type.
The second line is an arbitary signature of up to 8 ASCII characters.
The next two lines label the pins in order from 1-10 and then 11-20.
The special labels GND and VCC must be specified for power; and the special label NC must be specified for unused pins.

After labeling the pins we provide equations that compute the outputs from the inputs.

; equations start here
QAB = A & B
QCD = C
# D
QEF = E & /F
# F & /E
QG = /G

Note the following:

Equations must be in Disjunctive Normal Form, colloquially “sum of products”.
We express AND and OR with & and #, or with * and +. Best to choose one style and stick with it.
Inputs can be negated with /.
Equations can be broken across lines however you like, but it seems most common to have one product term per line.
Comments start with a ; and go to the end of the line. They cannot appear in the prelude.

The epilogue of our source file must contain the DESCRIPTION keyword, so you might as well go ahead and write a description. Our final source file is as follows:

logidemo.pld

GAL16V8
LOGIDEMO
A B C D E F G NC NC GND
NC NC NC NC NC QG QEF QCD QAB VCC
; equations start here
QAB = A & B
QCD = C
# D
QEF = E & /F
# F & /E
QG = /G
DESCRIPTION
Example GAL definition with several combinational logic gates.

You may have noticed that we never declare that we want simple operating mode, nor do we specify which pins are inputs and which are outputs. Intead GALasm infers these properties from the equations.

Assembly

Before we assemble our source we need to install GALasm. Download the repo, go into src, and make. The output is a single binary galasm that you can move wherever you want.

And now, we assemble:

$ galasm -v logidemo.pld
GALasm 2.1, Portable GAL Assembler
Copyright (c) 1998-2003 Alessandro Zummo. All Rights Reserved
Original sources Copyright (c) 1991-96 Christian Habermann
Assembler Phase 1 for "logidemo.pld"
Assembler Phase 2 for "logidemo.pld"
Defaulting to simple mode
GAL16V8; Operation mode: simple; Security fuse off
Assembling successfully completed.
$ _

If everything went well you will see something like the output above. Note that the next-to-last line identifies the operation mode as simple.

There are four output files:

File	Descripion
`logidemo.chp`	An ASCII-art picture of the IC, with our pin labels.
`logidemo.pin`	A text file with a table of pin types and labels.
`logidemo.fus`	Human-readable tables for the fuses that will be set in the GAL.
`logidemo.jed`	JEDEC file that we can actually program onto the GAL.

If things did not go well you may have been presented with an error message, and it might not make any sense. If the error is Error: Not enough free memory! it can mean a lot of things, including file not found. You’ll have to mess around and figure out what’s going on.

Programming

Now that we have our JEDEC file we can program the GAL with minipro. See the repo’s README for installation instructions; it’s available on many package managers. You will also need a TL866 or T48 programmer, and it needs to be plugged into your computer.

There are many variations of the GAL16V8, so check the list on minipro and see if yours shows up. Unless specified otherwise the package is DIP.

$ minipro -L GAL16V8
Found TL866II+ 04.2.123 (0x27b)
Warning: Firmware is out of date.
Expected 04.2.132 (0x284)
Found 04.2.123 (0x27b)
Device code: 02106811
Serial code: N95SXK8LUBRHLHXHQG4Y
USB speed: 12Mbps (USB 1.1)
GAL16V8
GAL16V8@SOIC20
GAL16V8A
GAL16V8A@SOIC20
GAL16V8B
GAL16V8B@SOIC20
GAL16V8C
GAL16V8C@SOIC20
GAL16V8D
GAL16V8D@SOIC20
$ _

GAL16V8D seems to be the common modern variant (sometimes there are other letters before the D).

To program, place your GAL in the programmer’s ZIF socket, aligning it according to the indication on the programmer. Then program, using your best guess for the part number:

$ minipro -p GAL16V8D -w logidemo.jed
Found TL866II+ 04.2.123 (0x27b)
Warning: Firmware is out of date.
Expected 04.2.132 (0x284)
Found 04.2.123 (0x27b)
Device code: 02106811
Serial code: N95SXK8LUBRHLHXHQG4Y
USB speed: 12Mbps (USB 1.1)
VPP=16V
Declared fuse checksum: 0x24B7 Calculated: 0x24B7 ... OK
Declared file checksum: 0x6B98 Calculated: 0x6B98 ... OK
JED file parsed OK
Erasing... 0.83Sec OK
Writing jedec file... 3.45Sec OK
Reading device... 0.09Sec OK
Verification OK
$ _

And that’s it. You can put the GAL on a breadboard and try it out, or keep reading and write a unit test. If programming fails, check the part number. If verification fails you may have a defective GAL. I just threw one in the trash for this reason.

Testing

We can write a minipro testcase with an XML file. Each <vector> below is a single test, specifying pins from 1 to 20, where 0 or 1 drives the pin and H or L are expected outputs. X means “don’t care”, and V/G are for power. Whitespace is ignored so I grouped the pins in a way that made sense to me.

logidemo.xml

<?xml version="1.0" encoding="utf-8"?>
<logicic>
 <database type="LOGIC">
 <custom name="whatever-you-want">
 <ic name="logidemo" type="5" voltage="5V" pins="20">

 <!-- AND gate at pins 1-2, output on 19 -->
 <vector> 00 XX XX X XXG XXXXX X X X L V </vector>
 <vector> 01 XX XX X XXG XXXXX X X X L V </vector>
 <vector> 10 XX XX X XXG XXXXX X X X L V </vector>
 <vector> 11 XX XX X XXG XXXXX X X X H V </vector>

 <!-- OR gate at pins 3-4, output on 18 -->
 <vector> XX 00 XX X XXG XXXXX X X L X V </vector>
 <vector> XX 01 XX X XXG XXXXX X X H X V </vector>
 <vector> XX 10 XX X XXG XXXXX X X H X V </vector>
 <vector> XX 11 XX X XXG XXXXX X X H X V </vector>

 <!-- XOR gate at pins 5-6, output on 17 -->
 <vector> XX XX 00 X XXG XXXXX X L X X V </vector>
 <vector> XX XX 01 X XXG XXXXX X H X X V </vector>
 <vector> XX XX 10 X XXG XXXXX X H X X V </vector>
 <vector> XX XX 11 X XXG XXXXX X L X X V </vector>

 <!-- NOT gate at pin 7, output on 16 -->
 <vector> XX XX XX 0 XXG XXXXX H X X X V </vector>
 <vector> XX XX XX 1 XXG XXXXX L X X X V </vector>

 </ic>
 </custom>
 </database>
</logicic>

Running the test with minipro shows no errors!

$ minipro -T -p logidemo --logicic logidemo.xml
Using overridden database file logidemo.xml
Found TL866II+ 04.2.123 (0x27b)
Warning: Firmware is out of date.
Expected 04.2.132 (0x284)
Found 04.2.123 (0x27b)
Device code: 02106811
Serial code: N95SXK8LUBRHLHXHQG4Y
USB speed: 12Mbps (USB 1.1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0000: 0 0 X X X X X X X G X X X X X X X X L V
0001: 0 1 X X X X X X X G X X X X X X X X L V
0002: 1 0 X X X X X X X G X X X X X X X X L V
0003: 1 1 X X X X X X X G X X X X X X X X H V
0004: X X 0 0 X X X X X G X X X X X X X L X V
0005: X X 0 1 X X X X X G X X X X X X X H X V
0006: X X 1 0 X X X X X G X X X X X X X H X V
0007: X X 1 1 X X X X X G X X X X X X X H X V
0008: X X X X 0 0 X X X G X X X X X X L X X V
0009: X X X X 0 1 X X X G X X X X X X H X X V
0010: X X X X 1 0 X X X G X X X X X X H X X V
0011: X X X X 1 1 X X X G X X X X X X L X X V
0012: X X X X X X 0 X X G X X X X X H X X X V
0013: X X X X X X 1 X X G X X X X X L X X X V
Logic test successful.
$ _

See this post about testing GALs for much more detail.

Other Features

Here are some other features that can be useful in simple mode. We will revisit these in later posts.

Feedback

Output pins provide feedback, which allows equations to mention outputs in their right-hand sides. For example, we could write equations that computes AND and OR and re-use these results to compute XOR.

QAND = A & B
QOR = A # B
QXOR = OR & /AND ; this equation mentions *outputs*

Feedback isn’t strictly necessary in simple mode, but it can save some repetition. When we get to registered mode we will use feedback to see prior values stored on the previous clock cycle, allowing for sequential logic.

Active-Low Pins

When we write equations we should really think of A and /A as meaning pin A is logically asserted or non-asserted, as opposed to thinking about physical voltage. Pins are active-high by default, but we can mark pins as active low when we declare pin labels by preceding the label with a /. For instance, making this single change to our example above effectively changes the first gate from AND to NAND.

A B C D E F G NC NC GND
NC NC NC NC NC QG QEF QCD /QAB VCC

We still refer to the pin as QAB in the rest of our code and it’s still asserted when A and B are both asserted, but assertion of QAB now means that the output will now be low rather than high. This also works for input pins; signals like “enable” are often active low.

The takeaway is that the choice of active-high or active-low is orthogogonal to your equations, which should be written in terms of assertion rather than physical logic level.

Pullups

The GAL16V8 provides active pullups for inputs and unassigned outputs, which allows (for example) an input to be connected to ground through a switch without an additional pull-up, becauese the floating input will be pulled to a logic high.

Pull-downs in the TL866 programmer seem to make it impossible to create truly floating inputs for tests; inputs marked with an X seem to have indeterminate logic values. So you need to pop the GAL into a breadboard to test this behavior. An 99¢ Logic Probe is great for this kind of thing.

Exercises

I encourge you to do some of these exercises (or make up some of your own) before moving on to the next post.

Change QCD to compute NOR and verify that the test fails. Fix the test.
Play around with active-low inputs and outputs until you’re confident you understand how they work.
Use a breadboard to check the behavior of floating inputs and unused outputs.
Modify equations to ouput AND, OR, and XOR for a single pair of inputs. Add some other relations like NAND. Feedback can be useful here.
Build a half adder, taking inputs A0 and A1 and producing output S for the sum and CO for the carry out.
Build a full adder, taking inputs A0 and A1 as well as CI for carry in, producing output S0 and S1 for the sum and CO for final carry out.
Build a 7-segment LED decoder, taking inputs D0 through D3 and producing outputs A through G for the LED segments such that the hexadecimal value of the 4-bit input is displayed as 0..F.

I Fixed the Air Conditioner

Sun, 13 Sep 2026 15:23:37 -0500

The AC went out last night and it was 82° inside this morning. All the HVAC contractors are super busy in Texas in the summer, and the best we could get was an appointment in three days. Not good enough. So I decided to give it a look myself.

I am not an electrician, I am a hobbyist. I have some experience with mains power but I am absolutely not qualified to tell you how to do this kind of thing. This is just a report about what I did and how it worked out.

It turns out the most common failure, a dead run capacitor, is easy to diagnose and easy to fix. My symptoms were:

The outside fan was spinning (this was unusual) but the compressor wasn’t running.
From time to time it would buzz for a couple seconds.

The problem is that without some capacitance to provide a phase shift in the current, the compressor motor can’t start or keep running. The fan motor seemed to get by ok for some reason. In any case, the big capacitor was rusty and bulging so I suspected that was the problem. Here’s what I did to diagnose.

Turned the air conditioning off at the thermostat.
Pulled out the cutoff breaker in the utility box for the AC unit.
Removed the service panel.
Checked AC voltage inside to be sure it was really disconnected.
Checked DC voltage across the capacitor, between the compressor terminal (3 prongs) and common (4 prongs), and between the fan terminal (2 prongs) and common. Normally these will be zero because the capacitor will drain through the motor coils, but if a coil is broken then the cap can contain a deadly amount of energy that needs to be discharged Watching the number go down while I hold multimeter probes across the terminals is the way I like to do this, rather than making a huge bang with a screwdriver. In my case all were zero.
Checked resistance across the same pairs of terminals. It was a few ohms for the compressor coil and a few tens of ohms for the fan coil, which seemed reasonable. They were not shorted, which made me fairly confident the motors were ok.
Checked capacitance across the same pairs of terminals. Nothing. Multimeter didn’t recognize that anything was connected. I took a photo of the wiring and then disconnected the cap and checked it on the LCR meter and it was just a few picofarads on both sides. Completely dead.

Now confident in my belief that the cap was bad I entered Lowe’s with a purposeful stride and walked to the capacitor section. However there was no such section so I strode back out and drove down the street to Home Depot, which did have a capacitor in the neighborhood of what I needed. Mine was a 45/5 and those were sold out, so I got a 50/5. A little extra can’t hurt. I assume.

Anyway, back home, plugged everything in and it worked. House is back down to 75° and everyone’s mood is much improved. Total cost was $25 and I am now a local hero.

Testing GALs with Minipro

Thu, 10 Sep 2026 10:37:58 -0500

I have used GALs a lot and always ended up testing them on breadboards with jumper wires, which doesn’t inspire a lot of confidence. But I recently discovered that I can write comprehensive test suites and run them with minipro. Here’s how it works.

Testing Common Logic ICs

Minipro has a test feature for common logic chips, which you invoke with -T. For example, if I put a 74LS14 hex inverter into my programmer I can test it by specifying part 7414.

$ minipro -p 7414 -T
Found TL866II+ 04.2.123 (0x27b)
Device code: 02106811
Serial code: N95SXK8LUBRHLHXHQG4Y
USB speed: 12Mbps (USB 1.1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0000: 0 H 0 H 0 H G H 0 H 0 H 0 V
0001: 1 L 1 L 1 L G L 1 L 1 L 1 V
Logic test successful.
$

This test has two cases, each of which is specified as a single line of tokens, one per pin:

0 and 1 specify input lines that will be driven low or high.
V and G specify the VCC and ground pins.
H and L specify expected outputs that will be checked.

Test cases are run in order from top to bottom (several times around to catch flaky tests).

This test and many others are defined in the logicic.xml file that minipro installs. On my machine it’s located in /opt/homebrew/share/minipro/. Here’s the specification for 7414 and a bunch of other inverters with the same pinout. Note that the <vector> elements exactly match the test output above.

<ic name="40106,7416,7414,7406,7405,7404,4584,4069" type="5" voltage="5V" pins="14">
 <vector id="00"> 0 H 0 H 0 H G H 0 H 0 H 0 V </vector>
 <vector id="01"> 1 L 1 L 1 L G L 1 L 1 L 1 V </vector>
</ic>

So the game here is to write our own test definitions.

Testing GALs

Here is a GALasm definition for a GAL16V8 that maintains five flip-flops that are set and reset by various input signals.

GAL16V8
GPIODEC
Clock NC ST3 ST2 ST1 RODT SODT RRST SRST GND
/OE /ODT /T3 /T2 /T1 /RST NC NC NC VCC
RST.R = SRST
+ RST * /RRST
ODT.R = /SRST * /RST * SODT
+ /SRST * /RST * ODT * /RODT
T1.R = /SRST * /RST * ST1
+ /SRST * /RST * T1
T2.R = /SRST * /RST * ST2
+ /SRST * /RST * T2
T3.R = /SRST * /RST * ST3
+ /SRST * /RST * T3
DESCRIPTION
This decodes the GPIO signals we care about.

And here is a custom test database with a specification for our GAL. We place this test in a new file of our choosing (we don’t need to modify the shared file).

test.xml

<?xml version="1.0" encoding="utf-8"?>
<logicic>
 <database type="LOGIC">
 <custom name="tpolecat industries">
 <ic name="gp1" type="5" voltage="5V" pins="20">

 <!-- Clock NC ST3 ST2 ST1 RODT SODT RRST SRST GND
 /OE /ODT /T3 /T2 /T1 /RST NC NC NC VCC -->

 <!-- This PLD is stateful and the initial state is unknown, so enter reset. -->
 <vector> C X 0 0 0 0 0 0 1 G 0 H H H H L X X X V </vector>

 <!-- None of the other inputs should work while in reset-->
 <vector> C X 0 0 0 0 1 0 0 G 0 H H H H L X X X V </vector>
 <vector> C X 0 0 1 0 0 0 0 G 0 H H H H L X X X V </vector>
 <vector> C X 0 1 0 0 0 0 0 G 0 H H H H L X X X V </vector>
 <vector> C X 1 0 0 0 0 0 0 G 0 H H H H L X X X V </vector>

 <!-- Exit reset -->
 <vector> C X 0 0 0 0 0 1 0 G 0 H H H H H X X X V </vector>

 <!-- Tests on, one by one. -->
 <vector> C X 0 0 1 0 0 0 0 G 0 H H H L H X X X V </vector>
 <vector> C X 0 1 0 0 0 0 0 G 0 H H L L H X X X V </vector>
 <vector> C X 1 0 0 0 0 0 0 G 0 H L L L H X X X V </vector>

 <!-- ODT on and then off, test bits should remain. -->
 <vector> C X 0 0 0 0 1 0 0 G 0 L L L L H X X X V </vector>
 <vector> C X 0 0 0 1 0 0 0 G 0 H L L L H X X X V </vector>

 <!-- ODT back on, just to ensure it clears below. -->
 <vector> C X 0 0 0 0 1 0 0 G 0 L L L L H X X X V </vector>

 <!-- Reset should clear everything -->
 <vector> C X 0 0 0 0 0 0 1 G 0 H H H H L X X X V </vector>
 <vector> C X 0 0 0 0 0 1 0 G 0 H H H H H X X X V </vector>

 <!-- We don't us Z output, but check anyway -->
 <vector> 0 X 0 0 0 0 0 0 0 G 1 Z Z Z Z Z Z Z Z V </vector>

 </ic>
 </custom>
 </database>
</logicic>

Note the following:

We specify name="gp1" and type="5" on the <ic> element. The name is arbitrary but it needs to be unique among the <ic> elements in the file. The type is required and is always 5.
All the <vector> elements in the shared database have an id element, but it’s ignored so I leave it out.
The test vectors use some tokens not discussed above:
- X means “don’t care, don’t read or drive this pin”. I’m using it for all the NC pins.
- C means “do a positive-going clock pulse before checking outputs”.
- Z is for expected high-impedance outputs.
Because this GAL implements sequential logic it’s important to place it in a known state as the first step in our tests, because the cases are run many times in a loop. Coming back around with a different set of flip-flops set can cause surprising behavior.

I run this test with minipro, passing my custom database with --logicic.

$ minipro -T --logicic test.xml -p gp1
Using overridden database file test.xml
Found TL866II+ 04.2.123 (0x27b)
Device code: 02106811
Serial code: N95SXK8LUBRHLHXHQG4Y
USB speed: 12Mbps (USB 1.1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0000: C X 0 0 0 0 0 0 1 G 0 H H H H L X X X V
0001: C X 0 0 0 0 1 0 0 G 0 H H H H L X X X V
0002: C X 0 0 1 0 0 0 0 G 0 H H H H L X X X V
0003: C X 0 1 0 0 0 0 0 G 0 H H H H L X X X V
0004: C X 1 0 0 0 0 0 0 G 0 H H H H L X X X V
0005: C X 0 0 0 0 0 1 0 G 0 H H H H H X X X V
0006: C X 0 0 1 0 0 0 0 G 0 H H H L H X X X V
0007: C X 0 1 0 0 0 0 0 G 0 H H L L H X X X V
0008: C X 1 0 0 0 0 0 0 G 0 H L L L H X X X V
0009: C X 0 0 0 0 1 0 0 G 0 L L L L H X X X V
0010: C X 0 0 0 1 0 0 0 G 0 H L L L H X X X V
0011: C X 0 0 0 0 1 0 0 G 0 L L L L H X X X V
0012: C X 0 0 0 0 0 0 1 G 0 H H H H L X X X V
0013: C X 0 0 0 0 0 1 0 G 0 H H H H H X X X V
0014: 0 X 0 0 0 0 0 0 0 G 1 Z Z Z Z Z Z Z Z V
Logic test successful.
$

And that’s it. Really nicely designed facility I think.

Test Vector Summary

The <vector> element contains a string of N tokens, where N is the number of pins.

Whitespace is ignored; you can pack the tokens together or spread them out however you like.
It’s an error if you don’t have enough tokens, but if you have too many it silently becomes confused and you will end up with weird test behavior. So double-check the token count if you can’t figure out what’s happening.

Here is a summary of the supported tokens.

Token	Meaning
`V`, `G`	Power pins, VCC and ground.
`0`, `1`	Input pin, drive low or high.
`L`, `H`, `Z`	Output pin, expect low, high, or high-impedance.
`C`, `K`	Clock pulse, positive-going and negative-going.
`X`	Don’t care. Don’t drive or read the pin.